This invention relates to a method of manufacturing a semiconductor device, and more particularly a semiconductor device where high voltage CMOS(complementary metal oxide semiconductor) transistors and low voltage CMOS transistors are installed on a same chip.
Standard power supply voltage of an LSI(large scale IC) used with a microcomputer is 5 V. But, LSIs for car control and LSIs for driving liquid crystal display panels, work under voltages higher than 10 V, and these LSIs must withstand at least 20 V and more.
Heretofore, aluminum gate CMOS process has been used for these high voltage LSIs, in which source-drain junctions are relatively deep(one to several .mu.m) and gate oxide films are thick(about 100 nm). This process is not adapted for miniaturization because a self alignment process is not applicable for forming a gate electrode and corresponding source-drain and because the source-drain junction is deep.
By a silicon gate CMOS process, which is mainly employed in current practices, a gate electrode and corresponding source-drain are produced by self alignment process making miniaturization and high speed performance feasible. High withstand voltage is obtained by providing a low density diffusion region in a drain domain for field intensity relaxation.
Using this silicon gate CMOS process and installing low voltage CMOS transistors for use as internal logics where miniaturization and high speed operation is required, and high voltage CMOS transistors for use as input and output circuits on a single chip, miniaturization, high speed operation, and high withstand voltage are made feasible, and these semiconductor devices can be used as LSIs for car control and LSIs for driving liquid crystal display panels.
Heretofore known process of manufacturing these silicon gate CMOS transistors will be briefly described;
(p-a) on a P type silicon substrate, N wells for low voltage P channel transistors and N wells for high voltage P channel transistors are formed by ion implantation and thermal diffusion, PA0 (p-b) field oxide films for isolation between elements are formed by selective oxidation, PA0 (p-c) gate oxide films are formed, PA0 (p-d) masking with photoresist film patterned by a photolithographic process, B ion is implanted in low voltage N channel transistor domains for controlling threshold voltage, PA0 (p-e) masking with photoresist film patterned by a photolithographic process, B ion is implanted in low voltage P channel transistor domains for controlling threshold voltage, PA0 (p-f) masking with photoresist film patterned by a photolithographic process, B ion is implanted in high voltage N channel transistor domains for controlling threshold voltage, PA0 (p-g) masking with photoresist film patterned by a photolithographic process, B ion is implanted in high voltage P channel transistor domains for controlling threshold voltage, PA0 (p-h) a polysilicon film is generated on the whole surface of the wafer, and gate electrodes of all transistors are formed by selective etching in a photolithographic process, PA0 (p-i) masking with the gate electrodes and photoresist film patterned by a photolithographic process, B ion is implanted in high voltage P channel transistor domains for forming low density diffusion regions working as field intensity relaxation regions, PA0 (p-j) masking with the gate electrodes and photoresist film patterned by a photolithographic process, P ion is implanted in high voltage N channel transistor domains for forming low density diffusion regions working as field intensity relaxation regions, PA0 (p-k) by heat treatment, a N.sup.- region for field intensity relaxation in each high voltage N channel transistor domain and a P.sup.- region for field relaxation in each high voltage P channel transistor domain are generated. PA0 (p-l) masking with photoresist films patterned by photolithographic processes, B ion is implanted in low voltage P channel transistor domains and high voltage P channel transistor domains, and As ion is implanted in low voltage N channel transistor domains and high voltage N channel transistor domains, PA0 (p-m) by heat treatment, all the sources and drains for every channel transistors are formed, the sources and the drains of low voltage transistors being formed by self alignment and the sources and drains of high voltage transistors are formed several .mu.m apart from the gate electrode, as are usually called offset gate type MOS transistors.
In the prior art method, there are four photolithographic processes repeated for ion implantation of controlling threshold voltages in each type of channels as described in (p-d), (p-e), (p-f) and (p-g), and two photolithographic processes repeated for forming low density diffusion regions as described in (p-i) and (p-j). In a photolithographic process, photoresist is painted on the whole surface, patterned for exposing selected areas, and removed after the implantation process is over. This takes a lot of time and cost, and the six repeated photolithographic process makes the whole manufacturing cost higher.